Silicide Formation Method of Semiconductor Device

专利摘要:
The present invention relates to a method for forming a silicide of a semiconductor device, the method comprising: providing a semiconductor substrate provided with a device isolation film; Forming a gate electrode and a low concentration impurity junction region formed of a first amorphous silicon film in an active region between the device isolation layers; Forming a second amorphous silicon film over the entirety; Forming a spacer on sidewalls of the gate electrode on which the second amorphous silicon film is formed; Forming a high concentration impurity junction region in the substrate region on both sides of the gate electrode; Patterning the second amorphous silicon film; Depositing a titanium film over the whole; And forming a titanium silicide film by performing a heat treatment process.
公开号:KR19980058438A
申请号:KR1019960077762
申请日:1996-12-30
公开日:1998-10-07
发明作者:이재성
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

Method for forming silicide of semiconductor device.
TECHNICAL FIELD This invention relates to the manufacturing method of a semiconductor device. Specifically, It is related with the low resistance self-aligned silicide formation method which can be used for 0.25 micrometer CMOS technology.
In general, in order to fabricate a high efficiency integrated CMOS device, it is essential that the gate electrode and source / drain diffusion region of the MOSFET have a low parasitic resistance. Accordingly, in order to lower the resistance of the gate electrode without changing the shape of the gate electrode, a gate electrode having a polyside structure in which metal silicide and polycrystalline silicon are laminated is used.
However, while the parasitic resistance of the gate electrode can be reduced in the above, the resistance in the source / drain regions still remains high, so recently, a new technique called salicide (self aligned silicide) has been required. .
Such a salicide technology forms silicides not only in the gate electrode but also in the source / drain junction region at the same time, so that parasitic resistance in these regions can be reduced, and thus, the salicide technique has been widely used in high-density CMOS technology.
Hereinafter, a method of forming titanium silicide according to the prior art will be described with reference to FIG. 1.
A gate oxide film 3 and a polysilicon film 4 for gate electrodes are formed on the semiconductor substrate 1 on which the device isolation film 1 is formed by a known method, and the polysilicon film 4 and the gate oxide film 3 are formed. ) To form a gate electrode, and then a low concentration impurity junction region 5 is formed, a spacer 6 is formed on the sidewall of the gate electrode, and then a high concentration impurity junction region is formed by a high concentration impurity ion implantation process ( 7) form.
Then, a titanium film (not shown) having a predetermined thickness is deposited on the whole, and the semiconductor substrate 1 on which the titanium film is deposited is heat-treated at a temperature of 600 ° C. or higher and an inert gas atmosphere such as nitrogen and argon. As a result, silicon and titanium in the gate electrode and the source / drain junction region react with each other to form a titanium silicide layer 8 having a predetermined thickness on the gate electrode and the source / drain junction region. The titanium silicide film 8 is not formed on the spacer 6.
Thereafter, titanium remaining on the titanium silicide layer without reacting with silicon is removed.
However, the prior art as described above, it is difficult to uniformly form the titanium silicide film on the silicon wiring having a narrow width of less than 0.5㎛, in this case, there is a problem that the resistance of the titanium silicide film is increased as the length of the silicon wiring is longer. In addition, when impurities such as As are heavily doped in the polysilicon film, As is diffused into the titanium silicide film during the silicide process, thereby increasing the contact resistance of the titanium silicide film.
Accordingly, the present invention prevents the diffusion of As doped into the polysilicon film for the gate electrode, and also reduces the contact resistance of the silicide by increasing the surface area of the silicon film on which the silicide is formed during the heat treatment process for forming the titanium silicide. It is an object of the present invention to provide a method for forming silicide of a semiconductor device.
1 is a cross-sectional view for explaining a silicide formation method of a semiconductor device according to the prior art.
2A to 2D are cross-sectional views illustrating a method of forming a silicide of a semiconductor device according to the present invention.
* Explanation of symbols for the main parts of the drawings
11 semiconductor substrate, 12 element isolation film, 13 gate oxide film, 14 first amorphous silicon film, 15 low concentration impurity junction region, 16 amorphous silicon film, 17 spacer, 18 high concentration impurity junction region, titanium Film, 20: titanium silicide film
The above object is to provide a semiconductor substrate provided with a device isolation film; Forming a gate electrode and a low concentration impurity junction region formed of a first amorphous silicon film in an active region between the device isolation layers; Forming a second amorphous silicon film over the entirety; Forming a spacer on sidewalls of the gate electrode on which the second amorphous silicon film is formed; Forming a high concentration impurity junction region in the substrate region on both sides of the gate electrode; Patterning the second amorphous silicon film; Depositing a titanium film over the whole; And performing a heat treatment process to form a titanium silicide film.
According to the present invention, a silicide film having excellent characteristics can be formed by forming a gate and a source / drain junction region, which are regions where silicide is to be formed, to have a stacked structure of a Ti film, an amorphous silicon film, and a polysilicon film doped with impurities.
EXAMPLE
Hereinafter, preferred embodiments of the present invention will be described in more detail.
According to the present invention, when a silicide film is formed on a silicon wiring having a narrow width, the silicon wiring has a narrow width and thus the silicide film is unstable, and As is doped into the silicon wiring by diffusion into the silicide film. In order to prevent an increase in contact resistance, a gate and a source / drain junction region of a MOSFET, which are regions in which silicide is to be formed, are formed to have a stacked structure of a Ti film, an amorphous silicon film, and a polysilicon film doped with impurities.
In the above, the amorphous silicon film prevents As doped from the polysilicon film from diffusing into the silicide film during the silicide process, and the diffusion of As may occur, but the amount is very small to suppress the increase in contact resistance of the silicide. You can. On the other hand, the amorphous silicon film is formed thin so that all of the silicide film can be consumed.
In addition, in order to increase the surface area where silicide can be formed, the silicon surface of the part where titanium is to be deposited should be made as porous as possible, so that the surface area of the part where silicide is formed is increased by using amorphous silicon having a lower density than single crystal silicon. As a result, the space in which the silicide is formed can be made relatively wide to form uniform silicide even on a silicon film having a narrow width.
Hereinafter, the silicide formation method of the semiconductor device of the present invention will be described in more detail with reference to FIGS. 2A to 2D.
Referring to FIG. 2A, after the gate oxide film 13 and the first amorphous silicon film 14 doped with As are formed on the semiconductor substrate 11 on which the device isolation film 12 is formed, the first amorphous silicon film ( 14 and the gate oxide film 13 are etched to form a gate electrode. Then, an oxidation process is performed to polycrystallize the amorphous silicon gate, and an oxide film (not shown) formed on the polycrystalline silicon gate is removed.
Subsequently, impurities are implanted into regions of the substrate 11 on both sides of the gate electrode to form the low concentration impurity junction region 15, and then the second amorphous silicon film 16 having a predetermined thickness is deposited on the entire upper portion. At this time, the second amorphous silicon film 16 is formed by an RF sputtering process to have a low density, and the thickness thereof is formed to a thickness of about 300 to 400 kHz.
Referring to FIG. 2B, a high concentration impurity junction region 17 is formed by ion implantation of impurities into a region of the semiconductor substrate 11, a spacer 18 is formed on the sidewall of the gate electrode by a known method, and then a heat treatment process. Is carried out. As a result of the heat treatment, the amorphous silicon adjacent to the spacer 18 has a Si—O bond, which prevents the gate and the source / drain from being shorted by the amorphous silicon during silicide formation.
Referring to FIG. 2C, the second amorphous silicon film is etched by a photolithography process, and a titanium film 19 having a predetermined thickness is formed on the entire upper portion.
Referring to FIG. 2D, the titanium silicide film 20 is formed by a two-step rapid heat treatment process, and the titanium and titanium nitride films that do not react with silicon are removed during the heat treatment process.
As described above, in the silicide formation method of the semiconductor device of the present invention, the gate and source / drain junction regions of the MOSFET, which are silicide formation regions, are formed to have a stacked structure of a Ti film, an amorphous silicon film, and a polysilicon film doped with impurities. As a result, a uniform titanium silicide film can be formed on the gate having a width of 0.25 μm, and the contact resistance of the silicide film due to the diffusion of As can be prevented to improve the reliability and characteristics of the semiconductor device.
Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

权利要求:
Claims (5)
[1" claim-type="Currently amended] Providing a semiconductor substrate provided with a device isolation film;
Forming a gate electrode and a low concentration impurity junction region formed of a first amorphous silicon film in an active region between the device isolation layers;
Forming a second amorphous silicon film over the entirety;
Forming a spacer on sidewalls of the gate electrode on which the second amorphous silicon film is formed;
Forming a high concentration impurity junction region in the substrate region on both sides of the gate electrode;
Patterning the second amorphous silicon film;
Depositing a titanium film over the whole; And
And forming a titanium silicide film by performing a heat treatment process.
[2" claim-type="Currently amended] 2. The method of claim 1, further comprising performing a heat treatment step to form a polycrystalline silicon gate after formation of the gate electrode made of the first amorphous silicon.
[3" claim-type="Currently amended] The method of claim 1, wherein the second amorphous silicon film is formed by a sputtering process.
[4" claim-type="Currently amended] 4. The method of claim 3, wherein the second amorphous silicon film is formed to a thickness of about 300 to 400 microns.
[5" claim-type="Currently amended] The method of claim 1, wherein the heat treatment process for forming the silicide film is a two-step rapid heat treatment process.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1996-12-30|Application filed by 김영환, 현대전자산업 주식회사

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1996-12-30|Priority to KR1019960077762A

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1998-10-07|Publication of KR19980058438A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019960077762A|KR19980058438A|1996-12-30|1996-12-30|Silicide Formation Method of Semiconductor Device|